There are a variety of different applications that can use memory circuits including, but not limited to, programmable logic devices (PLDs). PLDs are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay locked loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet, and so forth.
Some PLDs include enough components and functionality to effectively serve as an entire computer system on a single IC chip. PLDs with such functionality are sometimes referred to as a system on a chip (SOC). An SOC can include one or more processor circuits that execute software instructions in order to carry out different functions. Upon startup (e.g., hard-power on or hard reset), some of the earliest set of instructions executed by the SOC provide instructions for how to boot the SOC. For instance, the SOC can first execute a boot read only memory (ROM) that configures the SOC to load a first-stage boot loader (FSBL) image. The FSBL instructions can specify how peripheral functional blocks of the SOC are configured, control and implement a configuration bitstream, setup and run the operating system (OS), and other boot-related functions. Often, the boot image for an SOC can be loaded from a non-volatile memory, such as a read only memory (ROM) circuit.
As the size of the boot image used by SOCs increases, the size of the storage location for the boot image increases. The time required to load the boot image can also increase. Thus, the time before the SOC is fully-configured and operational can increase. The increased load time can be problematic in instances where it is desirable to have the SOC be available quickly, whether upon power-up or in similar situations. These and other problems can be problematic for SOC design and their use.